1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly, to a design for improving the testability of the semiconductor integrated circuit.
2. Description of Related Art
Known methods of testing the functions of semiconductor integrated circuits include a method employing scanning, a method employing built-in self test (BIST) circuits, and a method directly supplying or reading data from the outside of an objective semiconductor chip. A function test to be conducted on a semiconductor device having a memory must read and write a large amount of data to and from the device. An example of such a function test is a direct function test (DFT) conducted on, for example, a static random access memory (static RAM) such as a cache memory of a microprocessor, which needs no refreshing operation, and a dynamic RAM such as an embedded DRAM which requires refreshing operation.
In order to quickly read and write a large amount of data in the direct function test, a first related art prepares a direct-function-test bus dedicated to the direct function test separately from an internal bus serving as a system bus for normal operation. The first related art has a problem of requiring additional wiring resources and buffers. To cope with the problem, a second related art employs, as a direct-function-test bus, an internal bus serving as a system bus for normal operation. Generally, the system bus is divided into stages to transfer data at high speed during normal operation. Data is transferred from one stage to another in synchronization with a clock signal.
In a semiconductor device having such a system bus divided into stages, function modules formed in the semiconductor device are often connected to different stages of the system bus. When conducting a direct function test on the function modules, a tester arranged outside the semiconductor device must consider the differences in the stages to which the function modules are connected. This results in complicating test patterns and deteriorating testing efficiency. In particular, when the function modules are memories of the same function, the tester must test the function modules in different sequences to cope with the differences in the stages. This greatly deteriorates testing efficiency.